Discussion:
imx27: pinctrl: GPIO set output value failed
Chris Ruehl
2014-01-14 04:13:30 UTC
Permalink
Hi,

some kind of weired problem:
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.

running kernel 3.13-rc

Working OK
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin 0x9,
function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415004
offset 18 value 0x3
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register 0xf441500c
offset 18 value 0x0
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415010
offset 18 value 0x0
NOT Working
[ 1.553833] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin 0xa,
function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553889] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415004
offset 20 value 0x3
[ 1.553944] imx27-pinctrl 10015000.iomuxc: write: register 0xf441500c
offset 20 value 0x0
[ 1.553997] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415010
offset 20 value 0x0


GPIOs 0-31, platform/10015000.gpio, 10015000.gpio:
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi

***@gtsir20:~# echo 1 > /sys/class/gpio/gpio10/value
***@gtsir20:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/10015000.gpio, 10015000.gpio:
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi

pinctrl_userio1: userio1-1 {
fsl,pins = <
/* 2x GPIO in */
/* MX27_PAD_LD8__GPIO1_14 (in) */
/* MX27_PAD_LD10__GPIO1_16 (in) */
0x0e 0x032 0x0
0x10 0x032 0x0
/* 3x GPIO out */
/* UHF Enable */
MX27_PAD_LD3__GPIO1_9 0x0
MX27_PAD_LD4__GPIO1_10 0x0
MX27_PAD_LD6__GPIO1_12 0x0
/*
LED 1,2,3
*/
MX27_PAD_PS__GPIO1_26 0x0
MX27_PAD_CONTRAST__GPIO1_30 0x0
MX27_PAD_REV__GPIO1_24 0x0
...

I reviewed the pinctrl source but cannot find the problem.

Help needed.

Thanks
Chris
Chris Ruehl
2014-01-14 05:39:22 UTC
Permalink
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin 0x9,
function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
Post by Chris Ruehl
NOT Working
[ 1.553833] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0xa, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553889] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 20 value 0x3
[ 1.553944] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 20 value 0x0
[ 1.553997] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 20 value 0x0
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi
pinctrl_userio1: userio1-1 {
fsl,pins = <
/* 2x GPIO in */
/* MX27_PAD_LD8__GPIO1_14 (in) */
/* MX27_PAD_LD10__GPIO1_16 (in) */
0x0e 0x032 0x0
0x10 0x032 0x0
/* 3x GPIO out */
/* UHF Enable */
MX27_PAD_LD3__GPIO1_9 0x0
MX27_PAD_LD4__GPIO1_10 0x0
MX27_PAD_LD6__GPIO1_12 0x0
/*
LED 1,2,3
*/
MX27_PAD_PS__GPIO1_26 0x0
MX27_PAD_CONTRAST__GPIO1_30 0x0
MX27_PAD_REV__GPIO1_24 0x0
...
I reviewed the pinctrl source but cannot find the problem.
Help needed.
Thanks
Chris
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Markus Pargmann
2014-01-14 08:57:02 UTC
Permalink
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
Yes you are right, it is wrong by 0x4, pinctrl-imx1-core.c:
#define MX1_ICONFB 0x10

Can you send a patch?

Thanks,

Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Chris Ruehl
2014-01-14 09:13:25 UTC
Permalink
Post by Markus Pargmann
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
#define MX1_ICONFB 0x10
Can you send a patch?
Thanks,
Markus
Hi Markus,

I found the wrong define already and recompile the kernel, but still not
working for me. Very strange.
gpio9,13 and 14,16 as input works OK. Only this buggers 10 and 12 are
bugging around.

a) I replaced a debug output statement after the address correction when
the pin-id > 16 to get correct
address output. Here a preview of the patch.
b) add pin soft reset before set the gpio parameter.

diff --git a/drivers/pinctrl/pinctrl-imx1-core.c
b/drivers/pinctrl/pinctrl-imx1-core.c
index 17aecde..fbaa70e 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/delay.h>

#include "core.h"
#include "pinctrl-imx1.h"
@@ -45,9 +46,10 @@ struct imx1_pinctrl {
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x10
+#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
+#define MX1_SWR 0x3C
#define MX1_PUEN 0x40

#define MX1_PORT_STRIDE 0x100
@@ -97,13 +99,13 @@ static void imx1_write_2bit(struct imx1_pinctrl
*ipctl, unsigned int pin_id,
u32 old_val;
u32 new_val;

- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;

+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
@@ -334,6 +336,9 @@ static int imx1_pmx_enable(struct pinctrl_dev
*pctldev, unsigned selector,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);

+ imx1_write_bit(ipctl, pin_id, 1, MX1_SWR); /* Soft
reset the pin */
+ /* reset done within 6 cycles */
+ usleep_range(10000,20000);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);


I will do some more testing and send the patch after, OK for you?

Chris
Markus Pargmann
2014-01-15 08:56:35 UTC
Permalink
Hi Chris,
Post by Chris Ruehl
Post by Markus Pargmann
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
#define MX1_ICONFB 0x10
Can you send a patch?
Thanks,
Markus
Hi Markus,
I found the wrong define already and recompile the kernel, but still
not working for me. Very strange.
gpio9,13 and 14,16 as input works OK. Only this buggers 10 and 12
are bugging around.
a) I replaced a debug output statement after the address correction
when the pin-id > 16 to get correct
address output. Here a preview of the patch.
b) add pin soft reset before set the gpio parameter.
gpios 10 and 12 are working correctly with a previous pin soft reset?
Post by Chris Ruehl
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c
b/drivers/pinctrl/pinctrl-imx1-core.c
index 17aecde..fbaa70e 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include "core.h"
#include "pinctrl-imx1.h"
@@ -45,9 +46,10 @@ struct imx1_pinctrl {
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x10
+#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
+#define MX1_SWR 0x3C
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
@@ -97,13 +99,13 @@ static void imx1_write_2bit(struct imx1_pinctrl
*ipctl, unsigned int pin_id,
u32 old_val;
u32 new_val;
- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
@@ -334,6 +336,9 @@ static int imx1_pmx_enable(struct pinctrl_dev
*pctldev, unsigned selector,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
+ imx1_write_bit(ipctl, pin_id, 1, MX1_SWR); /* Soft
reset the pin */
This is over 80 lines, simply put the comment above. Would also be
great if you could add some more description here why a soft reset is
necessary. It is not listed in the reference manual, so this may be
confusing otherwise.
Post by Chris Ruehl
+ /* reset done within 6 cycles */
+ usleep_range(10000,20000);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
I will do some more testing and send the patch after, OK for you?
Yes that's ok. You could also seperate the ICONFB bugfix into a seperate
patch.

Regards,

Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Chris Ruehl
2014-01-15 09:28:59 UTC
Permalink
Post by Markus Pargmann
Hi Chris,
Post by Chris Ruehl
Post by Markus Pargmann
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
#define MX1_ICONFB 0x10
Can you send a patch?
Thanks,
Markus
Hi Markus,
I found the wrong define already and recompile the kernel, but still
not working for me. Very strange.
gpio9,13 and 14,16 as input works OK. Only this buggers 10 and 12
are bugging around.
a) I replaced a debug output statement after the address correction
when the pin-id > 16 to get correct
address output. Here a preview of the patch.
b) add pin soft reset before set the gpio parameter.
gpios 10 and 12 are working correctly with a previous pin soft reset?
I add the software reset for testing only. Its not change the behave and
therefore it will NOT be part of my patch.
Post by Markus Pargmann
Post by Chris Ruehl
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c
b/drivers/pinctrl/pinctrl-imx1-core.c
index 17aecde..fbaa70e 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include "core.h"
#include "pinctrl-imx1.h"
@@ -45,9 +46,10 @@ struct imx1_pinctrl {
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x10
+#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
+#define MX1_SWR 0x3C
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
@@ -97,13 +99,13 @@ static void imx1_write_2bit(struct imx1_pinctrl
*ipctl, unsigned int pin_id,
u32 old_val;
u32 new_val;
- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
@@ -334,6 +336,9 @@ static int imx1_pmx_enable(struct pinctrl_dev
*pctldev, unsigned selector,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
+ imx1_write_bit(ipctl, pin_id, 1, MX1_SWR); /* Soft
reset the pin */
This is over 80 lines, simply put the comment above. Would also be
great if you could add some more description here why a soft reset is
necessary. It is not listed in the reference manual, so this may be
confusing otherwise.
(as mentioned will not commit because not change anything)
Post by Markus Pargmann
Post by Chris Ruehl
+ /* reset done within 6 cycles */
+ usleep_range(10000,20000);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
I will do some more testing and send the patch after, OK for you?
Yes that's ok. You could also seperate the ICONFB bugfix into a seperate
patch.
Regards,
Markus
I'd fresh cloned the linux-next and will prepare a patch from 3.13-rc8
tomorrow.
with fix the ICONFB and debug output.
(I'd have bloody meetings today eat up all my time .. )

Chris
Chris Ruehl
2014-01-17 07:01:48 UTC
Permalink
Post by Markus Pargmann
Hi Chris,
Post by Chris Ruehl
Post by Markus Pargmann
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
#define MX1_ICONFB 0x10
Can you send a patch?
Thanks,
Markus
Hi Markus,
I found the wrong define already and recompile the kernel, but still
not working for me. Very strange.
gpio9,13 and 14,16 as input works OK. Only this buggers 10 and 12
are bugging around.
a) I replaced a debug output statement after the address correction
when the pin-id > 16 to get correct
address output. Here a preview of the patch.
b) add pin soft reset before set the gpio parameter.
gpios 10 and 12 are working correctly with a previous pin soft reset?
Post by Chris Ruehl
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c
b/drivers/pinctrl/pinctrl-imx1-core.c
index 17aecde..fbaa70e 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include "core.h"
#include "pinctrl-imx1.h"
@@ -45,9 +46,10 @@ struct imx1_pinctrl {
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x10
+#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
+#define MX1_SWR 0x3C
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
@@ -97,13 +99,13 @@ static void imx1_write_2bit(struct imx1_pinctrl
*ipctl, unsigned int pin_id,
u32 old_val;
u32 new_val;
- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
@@ -334,6 +336,9 @@ static int imx1_pmx_enable(struct pinctrl_dev
*pctldev, unsigned selector,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
+ imx1_write_bit(ipctl, pin_id, 1, MX1_SWR); /* Soft
reset the pin */
This is over 80 lines, simply put the comment above. Would also be
great if you could add some more description here why a soft reset is
necessary. It is not listed in the reference manual, so this may be
confusing otherwise.
Post by Chris Ruehl
+ /* reset done within 6 cycles */
+ usleep_range(10000,20000);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
I will do some more testing and send the patch after, OK for you?
Yes that's ok. You could also seperate the ICONFB bugfix into a seperate
patch.
Regards,
Markus
Hi Markus,

Its very confusing what the mxc driver is doing, I'd enabled the
debugging and the
kernel spits out this:

***@gtsir20:~# dmesg | tail -2
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
***@gtsir20:~# echo 0 > /sys/class/gpio/gpio9/value
***@gtsir20:~# echo 1 > /sys/class/gpio/gpio9/value
***@gtsir20:~# dmesg | tail -6
[ 40.753967] Bluetooth: RFCOMM socket layer initialized
[ 40.759277] Bluetooth: RFCOMM ver 1.11
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
[ 3120.825803] mxc: switch GPIO 9 to high trigger
[ 3126.281689] mxc: switch GPIO 9 to low trigger

But GPIO9 is defined as output not as IRQ
and act as output so enable/disable an external device
connected to it.

Why its sets the interrupts?

When I switch gpio10/12 on/off there is no output and its defined
the same way as gpio9

pinctrl_userio1: userio1-1 {
fsl,pins = <
/* 2x GPIO in */
MX27_PAD_LD8__GPIO1_14 0x0
MX27_PAD_LD10__GPIO1_16 0x0
/* 3x GPIO out
MX27_PAD_LD3__GPIO1_9 0x0
MX27_PAD_LD4__GPIO1_10 0x0
MX27_PAD_LD6__GPIO1_12 0x0 */
0x09 0x036 0x0
0x0a 0x036 0x0
0x0c 0x036 0x0

(linux-next-20140115)

Chris
Markus Pargmann
2014-01-17 08:55:05 UTC
Permalink
Hi,

I added Fabio and Shawn to cc, they may know something about this
problem.
Post by Chris Ruehl
Post by Markus Pargmann
Hi Chris,
Post by Chris Ruehl
Post by Markus Pargmann
Hi,
Post by Chris Ruehl
Just fall over the Reference manual for the GPIO ports.
Seams the iconfb0 is not addressed right.
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
Table 6.1 of the imx27 reference manual says (Page 6-5,6-6)
Post by Chris Ruehl
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin
0x9, function 0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415004 offset 18 value 0x3
PTA_OCR1 1001_5004 OK
Post by Chris Ruehl
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register
0xf441500c offset 18 value 0x0
PTA_ICONFA1 1001_500C OK
Post by Chris Ruehl
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register
0xf4415010 offset 18 value 0x0
PTA_ICONFB1 1001_5014 ---> 0xf4415010 seams the wrong address
1001_5010 is the PTA_ICONFA2
#define MX1_ICONFB 0x10
Can you send a patch?
Thanks,
Markus
Hi Markus,
I found the wrong define already and recompile the kernel, but still
not working for me. Very strange.
gpio9,13 and 14,16 as input works OK. Only this buggers 10 and 12
are bugging around.
a) I replaced a debug output statement after the address correction
when the pin-id > 16 to get correct
address output. Here a preview of the patch.
b) add pin soft reset before set the gpio parameter.
gpios 10 and 12 are working correctly with a previous pin soft reset?
Post by Chris Ruehl
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c
b/drivers/pinctrl/pinctrl-imx1-core.c
index 17aecde..fbaa70e 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include "core.h"
#include "pinctrl-imx1.h"
@@ -45,9 +46,10 @@ struct imx1_pinctrl {
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x10
+#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
+#define MX1_SWR 0x3C
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
@@ -97,13 +99,13 @@ static void imx1_write_2bit(struct imx1_pinctrl
*ipctl, unsigned int pin_id,
u32 old_val;
u32 new_val;
- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
@@ -334,6 +336,9 @@ static int imx1_pmx_enable(struct pinctrl_dev
*pctldev, unsigned selector,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
+ imx1_write_bit(ipctl, pin_id, 1, MX1_SWR); /* Soft
reset the pin */
This is over 80 lines, simply put the comment above. Would also be
great if you could add some more description here why a soft reset is
necessary. It is not listed in the reference manual, so this may be
confusing otherwise.
Post by Chris Ruehl
+ /* reset done within 6 cycles */
+ usleep_range(10000,20000);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
I will do some more testing and send the patch after, OK for you?
Yes that's ok. You could also seperate the ICONFB bugfix into a seperate
patch.
Regards,
Markus
Hi Markus,
Its very confusing what the mxc driver is doing, I'd enabled the
debugging and the
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
[ 40.753967] Bluetooth: RFCOMM socket layer initialized
[ 40.759277] Bluetooth: RFCOMM ver 1.11
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
[ 3120.825803] mxc: switch GPIO 9 to high trigger
[ 3126.281689] mxc: switch GPIO 9 to low trigger
But GPIO9 is defined as output not as IRQ
and act as output so enable/disable an external device
connected to it.
Why its sets the interrupts?
When I switch gpio10/12 on/off there is no output and its defined
the same way as gpio9
For gpio9 you only see the trigger settings, not the value setup.
Perhaps it doesn't try to set the irq stuff for gpio10/12. You could
have a look into the registers to see if they maybe have the correct
gpio settings and something else is wrong.

Regards,

Markus
Post by Chris Ruehl
pinctrl_userio1: userio1-1 {
fsl,pins = <
/* 2x GPIO in */
MX27_PAD_LD8__GPIO1_14 0x0
MX27_PAD_LD10__GPIO1_16 0x0
/* 3x GPIO out
MX27_PAD_LD3__GPIO1_9 0x0
MX27_PAD_LD4__GPIO1_10 0x0
MX27_PAD_LD6__GPIO1_12 0x0 */
0x09 0x036 0x0
0x0a 0x036 0x0
0x0c 0x036 0x0
(linux-next-20140115)
Chris
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Chris Ruehl
2014-01-20 04:32:22 UTC
Permalink
Post by Chris Ruehl
Hi Markus,
Its very confusing what the mxc driver is doing, I'd enabled the
debugging and the
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
[ 40.753967] Bluetooth: RFCOMM socket layer initialized
[ 40.759277] Bluetooth: RFCOMM ver 1.11
[ 43.683766] mxc: set GPIO 9 to high trigger
[ 44.766186] mxc: switch GPIO 9 to low trigger
[ 3120.825803] mxc: switch GPIO 9 to high trigger
[ 3126.281689] mxc: switch GPIO 9 to low trigger
But GPIO9 is defined as output not as IRQ
and act as output so enable/disable an external device
connected to it.
Why its sets the interrupts?
Works as designed!
I enabled the LED for GPIO9 (/sys/class/led/green/gpio = 9,
/sys/class/led/trigger = gpio)

sorry about the noise here.

Now I going to dump the registers - to see what if I can find the
GPIO10/12 bug.
Chris Ruehl
2014-01-22 04:21:12 UTC
Permalink
Hi,

after fix the imx_read_2bit() the registers show the expected values.
Ergo the problem must be in the gpiolib, my guess

pin 9 (MX27_PAD_LD3) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 10 (MX27_PAD_LD4) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 11 (MX27_PAD_LD5) GPIO 1, function 0, direction 0, oconf 3, iconfa 0, iconfb 0
pin 12 (MX27_PAD_LD6) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0

gain, gpio9 works gpio10,12 not response on the /sys/class/gpio/gpio10/value
changes.

Any Idea?
Post by Chris Ruehl
Hi,
Some GPIO's can modified via /sysfs others cannot
in my case gpio9 works, and gpio10,12 not.
The pinctrl debug out looks good to me.
running kernel 3.13-rc
Working OK
[ 1.553601] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin 0x9, function
0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553657] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415004 offset
18 value 0x3
[ 1.553712] imx27-pinctrl 10015000.iomuxc: write: register 0xf441500c offset
18 value 0x0
[ 1.553766] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415010 offset
18 value 0x0
NOT Working
[ 1.553833] imx27-pinctrl 10015000.iomuxc: imx1_pmx_enable, pin 0xa, function
0, gpio 1, direction 1, oconf 3, iconfa 0, iconfb 0
[ 1.553889] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415004 offset
20 value 0x3
[ 1.553944] imx27-pinctrl 10015000.iomuxc: write: register 0xf441500c offset
20 value 0x0
[ 1.553997] imx27-pinctrl 10015000.iomuxc: write: register 0xf4415010 offset
20 value 0x0
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
gpio-12 (sysfs ) out lo
gpio-14 (sysfs ) in hi
gpio-16 (sysfs ) in hi
gpio-24 (green ) out hi
gpio-26 (red ) out lo
gpio-30 (yellow ) out lo
gpio-31 (10024170.usbphy ) out hi
pinctrl_userio1: userio1-1 {
fsl,pins = <
/* 2x GPIO in */
/* MX27_PAD_LD8__GPIO1_14 (in) */
/* MX27_PAD_LD10__GPIO1_16 (in) */
0x0e 0x032 0x0
0x10 0x032 0x0
/* 3x GPIO out */
/* UHF Enable */
MX27_PAD_LD3__GPIO1_9 0x0
MX27_PAD_LD4__GPIO1_10 0x0
MX27_PAD_LD6__GPIO1_12 0x0
/*
LED 1,2,3
*/
MX27_PAD_PS__GPIO1_26 0x0
MX27_PAD_CONTRAST__GPIO1_30 0x0
MX27_PAD_REV__GPIO1_24 0x0
...
I reviewed the pinctrl source but cannot find the problem.
Help needed.
Thanks
Chris
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Uwe Kleine-König
2014-01-22 08:50:24 UTC
Permalink
Hello Chris,

just a few questions to maybe bring you forward in your debug session.
Post by Chris Ruehl
after fix the imx_read_2bit() the registers show the expected values.
Ergo the problem must be in the gpiolib, my guess
pin 9 (MX27_PAD_LD3) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 10 (MX27_PAD_LD4) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 11 (MX27_PAD_LD5) GPIO 1, function 0, direction 0, oconf 3, iconfa 0, iconfb 0
pin 12 (MX27_PAD_LD6) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
Can dump the gpio register space (e.g. using jtag or memedit)? Then try
something like:

dump register space
echo 1 > /sys/class/gpio/gpio10/value
dump register space again and compare with result from above

Feel free to share your results for additional pairs of eyes.

Do the gpios work in the boot loader?
Post by Chris Ruehl
gain, gpio9 works gpio10,12 not response on the
/sys/class/gpio/gpio10/value changes.
How do you diagnose "no response"? With a multimeter or software wise?
You are measuring the right pins, are you?

Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Chris Ruehl
2014-01-22 09:07:44 UTC
Permalink
Post by Uwe Kleine-König
Hello Chris,
just a few questions to maybe bring you forward in your debug session.
Post by Chris Ruehl
after fix the imx_read_2bit() the registers show the expected values.
Ergo the problem must be in the gpiolib, my guess
pin 9 (MX27_PAD_LD3) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 10 (MX27_PAD_LD4) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 11 (MX27_PAD_LD5) GPIO 1, function 0, direction 0, oconf 3, iconfa 0, iconfb 0
pin 12 (MX27_PAD_LD6) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
Can dump the gpio register space (e.g. using jtag or memedit)? Then try
memedit can download from your Web right, sadly I didn't have a jtag on
my CPU card.
Post by Uwe Kleine-König
dump register space
echo 1 > /sys/class/gpio/gpio10/value
dump register space again and compare with result from above
Feel free to share your results for additional pairs of eyes.
Do the gpios work in the boot loader?
I have a 2.6.22(*) kernel with and from early development from my board a
3.8.xx(**) which was able to set the gpio
(*) via /proc/..
(**) via /sys/class/..
Post by Uwe Kleine-König
Post by Chris Ruehl
gain, gpio9 works gpio10,12 not response on the
/sys/class/gpio/gpio10/value changes.
How do you diagnose "no response"? With a multimeter or software wise?
You are measuring the right pins, are you?
Best regards
Uwe
The pins routed to an opto-coupler and measured with multi-meter and LED

Chris
Uwe Kleine-König
2014-01-24 10:11:48 UTC
Permalink
Hello Chriss,

[expanded Cc: a bit]
Post by Chris Ruehl
Post by Uwe Kleine-König
Post by Chris Ruehl
after fix the imx_read_2bit() the registers show the expected values.
Ergo the problem must be in the gpiolib, my guess
pin 9 (MX27_PAD_LD3) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 10 (MX27_PAD_LD4) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 11 (MX27_PAD_LD5) GPIO 1, function 0, direction 0, oconf 3, iconfa 0, iconfb 0
pin 12 (MX27_PAD_LD6) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
Can dump the gpio register space (e.g. using jtag or memedit)? Then try
memedit can download from your Web right, sadly I didn't have a jtag
on my CPU card.
yeah, http://www.pengutronix.de/software/memedit/downloads/. I think
there are alternatives, too.

Can you confirm that:
# echo 0 > /sys/class/gpio/gpio9/value
# echo 0 > /sys/class/gpio/gpio10/value
# cat /sys/kernel/debug/gpio
...
gpio-9 (sysfs ) out lo
gpio-10 (sysfs ) out lo
...
# echo 1 > /sys/class/gpio/gpio9/value
# echo 1 > /sys/class/gpio/gpio10/value
# cat /sys/kernel/debug/gpio
...
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo

But still the pins work as expected, i.e. both are 0 after the first two
commands and both 1 at the end? Also, are the voltage levels OK?

In a different thread here on lakml
(http://thread.gmane.org/gmane.linux.ports.arm.kernel/295260/focus=295299)
it was suggested to implement a per-gpiochip flag to signal if the given
gpiochip can read from an output. If the above is right, we'd need a
per-gpio flag instead on i.MX27 (or not set it at all and so loose the
ability to read from the working pins).

Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Chris Ruehl
2014-01-27 02:17:07 UTC
Permalink
Hi Uwe,
Post by Uwe Kleine-König
Hello Chriss,
[expanded Cc: a bit]
Post by Chris Ruehl
Post by Uwe Kleine-König
Post by Chris Ruehl
after fix the imx_read_2bit() the registers show the expected values.
Ergo the problem must be in the gpiolib, my guess
pin 9 (MX27_PAD_LD3) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 10 (MX27_PAD_LD4) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
pin 11 (MX27_PAD_LD5) GPIO 1, function 0, direction 0, oconf 3, iconfa 0, iconfb 0
pin 12 (MX27_PAD_LD6) GPIO 1, function 0, direction 1, oconf 3, iconfa 0, iconfb 0
Can dump the gpio register space (e.g. using jtag or memedit)? Then try
memedit can download from your Web right, sadly I didn't have a jtag
on my CPU card.
yeah, http://www.pengutronix.de/software/memedit/downloads/. I think
there are alternatives, too.
# echo 0 > /sys/class/gpio/gpio9/value
# echo 0 > /sys/class/gpio/gpio10/value
# cat /sys/kernel/debug/gpio
...
gpio-9 (sysfs ) out lo
gpio-10 (sysfs ) out lo
...
# echo 1 > /sys/class/gpio/gpio9/value
# echo 1 > /sys/class/gpio/gpio10/value
# cat /sys/kernel/debug/gpio
...
gpio-9 (sysfs ) out hi
gpio-10 (sysfs ) out lo
But still the pins work as expected, i.e. both are 0 after the first two
commands and both 1 at the end? Also, are the voltage levels OK?
Yes confirm, the behave and voltage levels are OK.
Post by Uwe Kleine-König
In a different thread here on lakml
(http://thread.gmane.org/gmane.linux.ports.arm.kernel/295260/focus=295299)
it was suggested to implement a per-gpiochip flag to signal if the given
gpiochip can read from an output. If the above is right, we'd need a
per-gpio flag instead on i.MX27 (or not set it at all and so loose the
ability to read from the working pins).
Best regards
Uwe
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